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1 of 22 rev: 061306 features 8051-compatible microcontroller adapts to its task 32, 64, or 128kbytes of nonvolatile sram for program and/or data storage in-system programming via on-chip serial port capable of modifying its own program or data memory in the end system provides separate byte-wide bus for peripherals performs crc-16 check of nv ram memory high-reliability operation maintains all nonvolatile resources up to 10 years in the absence of v cc at room temperature power-fail reset early warning power-fail interrupt watchdog timer lithium backed memory remembers system state precision reference for power monitor fully 8051-compatible 128 bytes scratchpad ram two timer/counters on-chip serial port 32 parallel i/o port pins permanently powered real-time clock pin configuration description the ds2251t 128k soft microcontroller module is an 8051-compatible microcontroller module based on nonvolatile ram technology. it is designed for systems that need large quantities of nonvolatile memory. like other members of the secure microcontroller famil y, it provides full comp atibility with the 8051 instruction set, timers, serial port, and parallel i/o ports. by using nv ram instead of rom, the user can program, then reprogram the microcont roller while in-system. the application software can even change its own operation. this allows frequent software upgr ades, adaptive programs, customized systems, etc. in addition, by using nv ram, the ds2251t is ideal fo r data logging applications. the powerful real- time clock includes interrupts for time stamp and date. it keeps time to one-hundredth of s econds using its on-board 32khz crystal. ds2251t 128k soft microcontroller module www.maxim-ic.com 72 1 72-pin simm ds2251t
ds2251t 2 of 22 the ds2251t provides the benefits of nv ram without us ing i/o resources. between 32 kbytes and 128 kbytes of onboard nv ram are available. a non-multiple xed byte-wide address and data bus is used for memory access. this bus, which is available at th e connector, can perform all memory access and also provide decoded chip enables for off-board memory mapped peripherals. this leaves the 32 i/o port pins free for application use. the ds2251t provides high-reliability operation in portable systems or systems with unreliable power. these features include the ability to save the operat ing state, power-fail reset, power-fail interrupt, and watchdog timer. all nonvolatile memory and resource s are maintained for over 10 years at room temperature in the absence of power. a user loads programs into the ds2251t via its on-chip serial bootstrap loader. this function supervises the loading of software into nv ram, validates it, then becomes transparent to the user. software is stored in onboard cmos sram. using its intern al partitioning, the ds2251t can divide a common ram into user-selectable program and data segments. this partition can be sele cted at program loading time, but can be modified anytime later. the micr oprocessor will decode me mory access to the sram, access memory via its byte-wide bus and write-pro tect the memory portion designated as program (rom). operating information is contained in the secure micr ocontroller user?s guide. this data sheet provides ordering information, pinout, a nd electrical specifications. ordering information part ram size (kb) max crystal speed (mhz) timekeeping? ds2251t-32-16 32 16 yes ds2251t-32-16# 32 16 yes DS2251T-64-16 64 16 yes DS2251T-64-16# 64 16 yes ds2251t-128-16 128 16 yes ds2251t-128-16# 128 16 yes # denotes a rohs-compliant package that may c ontain lead exempt under the rohs requirements.
ds2251t 3 of 22 ds2251t block diagram figure 1
ds2251t 4 of 22 pin assignment pin name pin name pin name pin name 1 p1.0 19 xtal2 37 p0.2 55 intb 2 p1.1 20 gnd 38 p0.1 56 bd0 3 p1.2 21 p2.0 39 p0.0 57 bd1 4 p1.3 22 p2.1 40 v cc 58 bd2 5 p1.4 23 p2.2 41 ba0 59 bd3 6 p1.5 24 p2.3 42 ba1 60 bd4 7 p1.6 25 p2.4 43 ba2 61 bd5 8 p1.7 26 p2.5 44 ba3 62 bd6 9 rst 27 p2.6 45 ba4 63 bd7 10 p3.0/rxd 28 p2.7 46 ba5 64 r/ w 11 p3.1/txd 29 psen 47 ba6 65 pf 12 p3.2/ int0 30 ale 48 ba7 66 pe3 13 p3.3/ int1 31 prog 49 ba8 67 pe4 14 p3.4/t0 32 p0.7 50 ba9 68 intp 15 p3.5/t1 33 p0.6 51 ba10 69 inta 16 p3.6/ wr 34 p0.5 52 ba11 70 sqw 17 p3.7/ rd 35 p0.4 53 ba12 71 vrst 18 xtal1 36 p0.3 54 ba13 72 ba15 pin description pin description 39?32 p0.0?p0.7. general-purpose i/o port 0. this port is open-drain and cannot drive a logic 1. it requires external pullups. port 0 is also th e multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 1?8 p1.0?p1.7. general-purpose i/o port 1. 21?28 p2.0?p2.7. general-purpose i/o port 2. also serves as the msb of the expanded address bus. 10 p3.0/rxd. general-purpose i/o port pin 3.0. also serv es as the receive signal for the on- board uart. this pin should not be connected directly to a pc com port. 11 p3.1/txd. general-purpose i/o port pin 3.1. also serv es as the transmit signal for the on- board uart. this pin should not be connected directly to a pc com port. 12 p3.2/ int0 . general-purpose i/o port pin 3.2. also serves as the active low external interrupt 0. 13 p3.3/ int1 . general-purpose i/o port pin 3.3. also serves as the active low external interrupt 1. 14 p3.4/t0. general-purpose i/o port pin 3.4. also serves as the timer 0 input.
ds2251t 5 of 22 pin description 15 p3.5/t1. general-purpose i/o port pin 3.5. also serves as the timer 1 input. 16 p3.6/ wr . general-purpose i/o port pin. also serves as the write strobe for expanded bus operation. 17 p3.7/ rd . general-purpose i/o port pin. also serves as the read strobe for expanded bus operation. 9 rst. active high reset input. a logic 1 applied to th is pin will activate a reset state. this pin is pulled down internally, can be left unconnect ed if not used. an rc power-on reset circuit is not needed and is not recommended. 29 psen . program store enable. this active low signal is used to enable an external program memory when using the expanded bus. it is nor mally an output and should be unconnected if not used. 30 ale. address latch enable. used to de-multiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a ?373 type transparent latch. 19, 18 xtal2, xtal1. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amp lifier and xtal2 is the output. 20 gnd. logic ground. 40 v cc . +5v 72 ba15. monitor test point to reflect the logical value of a15. not need ed for memory access. 54?41 ba13?ba 0. byte-wide address bus bits 13?0. this bus is combined with the non- multiplexed data bus (bd7?bd0) to access onbo ard nv sram and off-board peripherals. peripheral decoding is performed using pe3 and pe4 . these are on 16k boundaries, so ba14 or ba15 are not needed. read/write access is controlled by r/ w . ba13?ba0 connect directly to memory-mapped peripherals. 63?56 bd7?bd0. byte-wide data bus bits 7?0. this 8-bit bi -directional bus is combined with the non-multiplexed address bus (ba14?ba0) to access on-board nv sram and off-board peripherals. 64 r/ w . read/write. this signal provides the wr ite enable to the srams on the byte-wide bus. it is controlled by the memory map and partition. the blocks selected as program (rom) will be write-protected. th is signal is also used for the write enable to off-board peripherals. 66 pe3 . peripheral enable 3. accesses data me mory between addresses 8000h and bfffh when the pes bit is set to a logic 1. pe3 is not lithium backed a nd can be connected to any type of peripheral function. 67 pe4 . peripheral enable 4. accesses data memo ry between addresses c000h and ffffh when the pes bit is set to a logic 1. pe4 is not lithium backed and can be connected to any type of peripheral function. 31 prog . invokes the bootstrap loader on a falling edge. this signal should be debounced so that only one edge is detecte d. if connected to ground, the micr o will enter bootstrap loading on power-up. this signal is pulled up internally.
ds2251t 6 of 22 pin description 71 vrst . this i/o pin (open-drain with internal pullup) indicates that the power supply (v cc ) has fallen below the v ccmin level and the micro is in a reset state. when this occurs, the ds2251t will drive this pin to a logic 0. because the micro is lithium backed, this signal is guaranteed even when v cc = 0v. because it is an i/o pin, it will also force a reset if pulled low externally. this allows multiple part s to synchronize their power-down resets. 65 pf . this output goes to a logic 0 to indicate that the micro ha s switched to lithium backup. it corresponds to v cc < v li . because the micro is lithium backed, this signal is guaranteed even when v cc = 0v. 55 intb . intb from the real-time clock. this output may be connected to a micro interrupt input. 68 intp . intp from the real-time clock. this open-drai n output requires a pullup and may be connected to a micro interrupt input. 69 inta . inta from the real-time clock. this output may be connected to a micro interrupt input. 70 sqw. square-wave output from the ds1283 real-t ime clock. can be programmed to output a 1024hz square wave. instruction set the ds2251t executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. as a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the ds2251t. a complete description of the instruction set and ope ration are provided in th e secure microcontroller user?s guide. memory organization figure 2 illustrates the memory map accessed by the ds2251t. the entire 64k of program and 64k of data are available to the byte-wide bus. this preserve s the i/o ports for applicati on use. the user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. any area not mapped into the nv ram is reached via the expanded bus on ports 0 and 2. an alternate configuration allows dynamic partitio ning of a 64k space as shown in figure 3. selecting pes = 1 provides access to the real-t ime clock on the ds2251t and enables pe3 and pe4 for peripheral access as shown in figure 4. these selections are ma de using special function registers. the memory map and its controls are covered in detail in the secure microcontroller user?s guide.
ds2251t 7 of 22 ds2251t memory map in non-pa rtitionable mode (pm = 1) figure 2 ds2251t memory map in part itionable mode (pm = 0) figure 3
ds2251t 8 of 22 ds2251t memory map with (pes = 1) figure 4 power management the ds2251t monitors v cc to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. it uses an internal ba nd-gap reference in determining the switch points. these are called v pfw , v ccmin , and v li , respectively. when v cc drops below v pfw , the ds2251t will perform an interrupt vector to locat ion 2bh if the power-fa il warning is enabled. fu ll processor operation continues regardless. when power falls further to v ccmin , the ds2251t invokes a rese t state. no further code execution will be performed unless power rises back above v ccmin . all decoded chip enables and the r/ w signal go to an inactive (logic 1) state. the vrst signal will be driven to a logic 0. v cc is still the power source at this time. when v cc drops further to below v li , internal circuitry will switch to the built-in lithium cell for power. the majority of intern al circuits will be disabled and the remaining nonvolatile states will be retained. pf will be driven to a logic 0. the secure microcontroller user?s guide has more information on this topic. the trip points v ccmin and v pfw are listed in the electrical specifications.
ds2251t 9 of 22 absolute maxi mum ratings voltage range on any pin relative to ground??????????????...-0.3v to (v cc + 0.5v) voltage range on v cc relative to ground???????????????????.-0.3v to +6.0v operating temperature range????????????????????????-40c to +85c storage temperature ( note 1 )???????????????????????..-55c to +125c soldering temperature????????????????????????+260c for 10 seconds this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. note 1: storage temperature is defined as the temperature of the device when v cc = 0v and v li = 0v. in this state the contents of sram are not battery backed and are undefined. dc characteristics (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) parameter symbol min typ max units notes input low voltage v il -0.3 +0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage rst, xtal1 prog v ih2 3.5 v cc +0.3 v 1 output low voltage at i ol = 1.6ma (ports 1, 2, 3, pf ) v ol1 0.15 0.45 v 1, 7 output low voltage at i ol = 3.2ma (ports 0, ale, psen , ba13:ba0, bd7:bd0, r/ w , pe3:pe4 ) v ol2 0.15 0.45 v 1 output high voltage at i oh = -80 a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage at i oh = -400 a (ports 0, ale, psen , pf , ba13:ba0, bd7:bd0, r/ w , pe3:pe4 ) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il -50 a transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) i tl -500 a input leakage current 0.45 < v in < v cc (port 0) i il 10 a rst pulldown resistor r re 40 150 k ? vrst pullup resistor r vr 4.7 k ? prog pullup resistor r pr 40 k ? power-fail warning voltage v pfw 4.25 4.37 4.50 v 1 minimum operating voltage v cc(min) 4.00 4.12 4.25 v 1 operating current at 16mhz i cc 45 ma 2
ds2251t 10 of 22 dc characteristics (continued) (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) parameter symbol min typ max units notes idle mode current at 12mhz i idle 7.0 ma 3 stop mode current i stop 80 a 4 pin capacitance c in 10 pf 5 with bat = 3.0v 4.0 4.25 reset trip point in stop mode with bat = 3.3v 4.4 4.65 v 1 ac characteristics?expanded bus mode timing specifications (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 1 oscillator frequency 1/t clk 1.0 16 (-16) mhz 2 ale pulse width t alpw 2t clk - 40 ns 3 address valid to ale low t avall t clk - 40 ns 4 address hold after ale low t avaav t clk - 35 ns at 12mhz 4t clk - 150 5 ale low to valid instruction in at 16mhz t allvi 4t clk - 90 ns 6 ale low to psen low t allpsl t clk - 25 ns 7 psen pulse width t pspw 3t clk - 35 ns at 12mhz 3t clk - 150 8 psen low to valid instruction in at 16mhz t pslvi 3t clk - 90 ns 9 input instr. hold after psen going high t psiv 0 ns 10 input instr. float after psen going high t psix t clk - 20 ns 11 address hold after psen going high t psav t clk - 8 ns at 12mhz 5t clk - 150 12 address valid to valid instruction in at 16mhz t avvi 5t clk - 90 ns 13 psen low to address float t pslaz 0 ns 14 rd pulse width t rdpw 6t clk - 100 ns 15 wr pulse width t wrpw 6t clk - 100 ns at 12mhz 5t clk - 165 16 rd low to valid data in at 16mhz t rdldv 5t clk - 105 ns 17 data hold after rd high t rdhdv 0 ns 18 data float after rd high t rdhdz 2t clk - 70 ns 19 ale low to valid data in at 12mhz t allvd 8 clk - 150 ns
ds2251t 11 of 22 ac characteristics?expanded bus mode timing specifications (continued) (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units at 12mhz 8 clk - 150 19 ale low to valid data in at 16mhz t allvd 8t clk - 90 ns at 12mhz 9t clk - 165 20 valid address to valid data in at 16mhz t avdv 9t clk - 105 ns 21 ale low to rd or wr low t allrdl 3t clk -50 3t clk + 50 ns 22 address valid to rd or wr low t avrdl 4t clk -130 ns 23 data valid to wr going low t dvwrl t clk - 60 ns at 12mhz 7t clk - 150 24 data valid to wr high at 16mhz t dvwrh 7t clk - 90 ns 25 data valid after wr high t wrhdv t clk - 50 ns 26 rd low to address float t rdlaz 0 ns 27 rd or wr high to ale high t rdhalh t clk - 40 t clk + 50 ns expanded program memory read cycle
ds2251t 12 of 22 expanded data memory read cycle
ds2251t 13 of 22 expanded data memory write cycle
ds2251t 14 of 22 ac characteristics?ex ternal clock drive (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units at 12mhz 20 28 external clock high time at 16mhz t clkhpw 15 ns at 12mhz 20 29 external clock low time at 16mhz t clklpw 15 ns at 12mhz 20 30 external clock rise time at 16mhz t clkr 15 ns at 12mhz 20 31 external clock fall time at 16mhz t clkf 15 ns external clock timing
ds2251t 15 of 22 ac characteristics?po wer cycle timing (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 32 slew rate from v ccmin to 3.3v t f 130 s 33 crystal startup time t csu (note 6) 34 power-on reset delay t por 21,504 t clk power cycle timing
ds2251t 16 of 22 ac characteristics?serial port timing: mode 0 (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 35 serial port cycle time t spclk 12t clk s 36 output data setup to rising clock edge t doch 10t clk - 133 ns 37 output data hold after rising clock edge t chdo 2t clk - 117 ns 38 clock rising edge to input data valid t chdv 10t clk - 133 ns 39 input data hold afte r rising clock edge t chdiv 0 ns serial port timing: mode 0
ds2251t 17 of 22 ac characteristics?parall el program load timing (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 41 pulse width of pe 3-4 t cepw 4t clk - 35 ns 45 byte-wide address hold after pe 3-4 high during movx t cehda 4t clk - 30 ns 46 delay from byte-wide address valid pe 3-4 low during movx t celda 4t clk - 35 ns 47 byte-wide data setup to pe 3-4 high during movx (read) t daceh 1t clk + 40 ns 48 byte-wide data hold after pe 3-4 high during movx (read) t cehdv 10 ns 49 byte-wide address valid to r/ w active during movx (write) t avrwl 3t clk - 35 ns 50 delay from r/ w low to valid data out during movx (write) t rwldv 20 ns 51 valid data out hold time from pe 3-4 high t cehdv 1t clk - 15 ns 52 valid data out hold time from r/ w high t rwhdv 0 ns 53 write pulse width (r/ w low time) t rwlpw 6t clk - 20 ns byte-wide bus timing
ds2251t 18 of 22 rpc ac characteristics?dbb read (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 54 cs , a 0 setup to rd t ar 0 ns 55 cs , a 0 hold after rd t ra 0 ns 56 rd pulse width t rr 160 ns 57 cs , a 0 to data out delay t ad 130 ns 58 rd to data out delay t rd 0 130 ns 59 rd to data float delay t rdz 85 ns rpc ac characteristics?dbb write (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 60 cs , a 0 setup to wr t aw 0 ns 61a cs , hold after wr t wa 0 ns 61b a 0 , hold after wr t wa 20 ns 62 wr pulse width t ww 20 ns 63 data setup to wr t dw 130 ns 64 data hold after wr t wd 20 ns ac characteristics?dma (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 65 dack to wr or rd t acc 0 ns 66 rd or wr to dack t cac 0 ns 67 dack to data valid t acd 0 130 ns 68 rd or wr to drq cleared t crq 110 ns ac characteristics? prog (v cc = 5v 10%, t a = 0 ? c to +70 ? c.) # parameter symbol min max units 69 prog low to active t pra 48 clks 70 prog high to inactive t pri 48 clks
ds2251t 19 of 22 rpc timing mode 16 rpc timing mode 16 (continued)
ds2251t 20 of 22 notes: 1. all voltages are referenced to ground. 2. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf =10ns, v il = 0.5v; xtal2 disconnected; rst = port0 = v cc . 3. idle mode i idle is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; port0 = v cc , rst = v ss . 4. stop mode i stop is measured with all output pins disconnected; port0 = v cc ; xtal2 not connected; rst = xtal1 = v ss . 5. pin capacitance is measured w ith a test frequency?1mhz, t a = +25c. 6. crystal startup time is the time required to get the mass of the crystal into vi brational motion from the time that power is first applied to the circuit un til the first clock pulse is produced by the on-chip oscillator. the user should check with the crystal vendor for a worst-case specification on this time. 7. pf pin operation is specified with v bat 3.0v.
ds2251t 21 of 22 package drawing pkg inches dim min max a 4.245 4.255 b 3.979 3.989 c 0.995 1.005 d 0.395 0.405 e 0.245 0.255 f 0.050 bsc g 0.075 0.085 h 0.245 0.255 i 1.750 bsc j 0.120 0.130 k 2.120 2.130 l 2.245 2.255 m 0.057 0.067 n - 0.275 o - 0.145 p 0.047 0.054
ds2251t 22 of 22 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. data sheet revision summary the following represent the key differences between 12/13/95 and 08/13/96 version of the ds2251t data sheet. please review this summary carefully. 1. change v cc slew rate definition to reference 3.3v instead of v li . 2. add minimum value to pcb thickness. the following represent the key differences between 08/15/96 and 05/29/97 version of the ds2251t data sheet. please review this summary carefully. 1. pf signal moved from v ol2 test specification to v ol1 . (pcnd73001) the following represent the key differences between 05/28/97 and 11/08/99 version of the ds2251t data sheet. please review this summary carefully. (pcn i80903) 1. correct absolute maximum ratings to re flect changes to ds5001fp microprocessor. 2. add note clarifying that sram contents are not defined under storage temperature conditions. the following represent the key differences between 11/08/99 and 01/18/00 version of the ds2251t data sheet. please review this summary carefully. 1. document converted from in terleaf to microsoft word. the following represent the key differences between 01/18/00 and 06/13/06 version of the ds2251t data sheet. please review this summary carefully. 1. updated reference in features (high-reliability operation) to 10-year nv ram data life to include room temperature caveat. 2. added rohs-compliant packages to ordering information table. 3. replaced references to ?secure microcontroller da ta book? with ?secure microcontroller user?s guide.?

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